Regviz

Microchip Technology /ATSAME70Q19 /SCB /SCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMV71J20/SCB/SCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VALUE_0)SLEEPONEXIT 0 (VALUE_0)SLEEPDEEP 0 (VALUE_0)SEVONPEND

SEVONPEND=VALUE_0, SLEEPONEXIT=VALUE_0, SLEEPDEEP=VALUE_0

Description

System Control Register

Fields

SLEEPONEXIT

Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state

0 (VALUE_0): o not sleep when returning to Thread mode

1 (VALUE_1): enter sleep, or deep sleep, on return from an ISR
SLEEPDEEP

Provides a qualifying hint indicating that waking from sleep might take longer

0 (VALUE_0): sleep

1 (VALUE_1): deep sleep
SEVONPEND

Determines whether an interrupt transition from inactive state to pending state is a wakeup event

0 (VALUE_0): only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded

1 (VALUE_1): enabled events and all interrupts, including disabled interrupts, can wakeup the processor

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data